Clock networks provide timing signals in logic devices, such as processors, digital signal processors, application specific integrated circuits (ASICs), and communication circuits. Many processors, digital signal processors, ASICs, and communication circuits include millions of logic nodes. In a logic device having millions of logic nodes, a clock network delivers thousands of timing signals to the millions of logic nodes. Each timing signal must arrive at a particular logic node within a specified time interval which is typically on the order of pico-seconds. The arrival time of these timing signals at each of the millions of logic nodes is critical to the correct operation of the logic device. If a timing signal does not arrive at a logic node within its assigned time interval, the logic device fails. If the logic device is embedded in a car, a train, or a plane and the logic device fails, the car, train, or plane may also fail.
The process of manufacturing and testing a logic device is a long, slow process. After a logic device is fabricated, it is electronically tested. To electronically test a logic device, signals at an output port of the logic device are monitored while a sequence of data signals and clock signals is provided at an input port of the logic device. If the monitored signals do not correspond to the input data signals, then the logic device fails the electronic test. After a logic device fails an electronic test, the logic device is analyzed to identify the reason for the failure. In many cases, logic devices fail because a clock signal arrives at a clock node of a data storage device before the corresponding data signal arrives at a data node of the storage device. To correct such defects in a logic device, the logic device is redesigned to speed up the data signal or to slow down the clock signal. Circuits are often added to the logic device to slow down the clock signals. After the logic device is redesigned, it is fabricated again using the same long, slow process that was used to manufacture the original device.
A trend in the integrated circuit industry is to design more complex logic devices. In more complex logic devices, the number of data storage devices increase and the number of clock signals increase. With more data storage devices and more clock signals, the number of failures resulting from clock signals being skewed with respect to data signals also increase. Increasing the number of failures increases the time required to analyze the failures and to re-manufacture the logic devices, which increases the product development cycle time and the cost of the logic device.
For these and other reasons there is a need for the present invention.